This invention relates to microelectronic devices and fabrication methods therefor, and more particularly to integrated circuit field effect transistors and fabrication methods therefor.
Integrated circuit field effect transistors are widely used in microelectronic devices such as logic, memory and/or microprocessor devices. As is well known to those having skill in the art, an integrated circuit field effect transistor includes spaced apart source and drain regions in an integrated circuit substrate, such as a silicon semiconductor substrate, and an insulated gate on the integrated circuit substrate between the spaced apart source and drain regions. The insulated gate includes an insulating layer on the integrated circuit substrate and a gate electrode on the insulating layer opposite the integrated circuit substrate. The source and drain regions may be formed by implanting dopants into the substrate, thereby defining a channel region therebetween, beneath the gate electrode. Insulated gate field effect transistors also are referred to as MOS transistors or MOSFETs.
The gate electrode of an integrated circuit field effect transistor generally comprises doped polysilicon that may be doped, for example, with an n-type impurity, such as phosphorus or arsenic. Unfortunately, since polysilicon may have a rough surface morphology, it may be difficult to pattern a polysilicon layer to provide a polysilicon gate electrode.
Accordingly, it has been proposed to form a gate electrode using amorphous silicon that can have a smoother surface morphology than that of polysilicon. For example, as shown in FIG. 1, a gate insulating layer 53, such as silicon dioxide is formed on an integrated circuit substrate 51, such as a monocrystalline silicon substrate. An amorphous silicon layer 55 then is formed on the gate insulating layer 53 opposite the substrate 51. Also see U.S. Pat. No. 4,479,831 to Sandow et al. entitled Method of Making Low Resistance Polysilicon Gate Transistors and Low Resistance Interconnections Therefore Via Gas Deposited In-Situ Doped Amorphous Layer and Heat-Treatment and U.S. Pat. No. 5,563,093 to Koda et al. entitled Method of Manufacturing FET Semiconductor Devices With Polysilicon Gate Having Large Grain Sizes.
After forming and patterning the amorphous silicon layer 55, a thermal treatment generally is performed to convert the amorphous silicon gate 55 into polysilicon. Unfortunately, during the thermal treatment, stresses 57 may be formed in the polysilicon gate, which may lead to defects 59 in the gate insulating layer 53. These defects may cause the leakage current of the field effect transistor to unduly increase, and can lead to failure of the integrated circuit field effect transistor.
Attempts have been made to overcome the introduction of defects into the gate electrode. For example, see U.S. Pat. No. 5,614,428 to Kapoor entitled Process and Structure for Reduction of Channeling During Implantation of Source and Drain Region in Formation of MOS Integrated Circuit Structures, and U.S. Pat. No. 5,837,598 to Aronowitz et al. entitled Diffusion Barrier for Polysilicon Gate Electrode of MOS Device in Integrated Circuit Structure, and Method of Making Same. Notwithstanding these and other attempts, it still is desirable to provide improved methods of forming gates for integrated circuit field effect transistors and integrated circuit field effect transistors so formed.
It therefore is an object of the present invention to provide improved methods of fabricating gates of integrated circuit field effect transistors, and integrated circuit field effect transistors so fabricated.
It is another object of the present invention to provide integrated circuit field effect transistor gates that can be patterned effectively, and fabrication methods therefor.
It is yet another object of the present invention to provide gates and gate fabrication methods for integrated circuit field effect transistors that can reduce defects in an underlying gate insulating layer during fabrication of the field effect transistor.
These and other objects may be provided, according to the present invention, by forming a polysilicon layer on a gate insulating layer opposite an integrated circuit substrate, forming an amorphous impurity layer on the polysilicon layer opposite the gate insulating layer, and forming an amorphous silicon layer on the amorphous impurity layer opposite the polysilicon layer. The amorphous silicon layer, the amorphous impurity layer and the polysilicon layer are patterned to define a gate electrode pattern. The polysilicon layer, the amorphous impurity layer and the amorphous silicon layer then are converted into a polysilicon gate having a first surface adjacent the gate insulating layer, a second surface opposite the gate insulating layer, and a buried doped layer within the polysilicon gate electrode that is spaced apart from the first and second surfaces thereof. The converting preferably takes place by thermally treating the gate electrode pattern. By using amorphous silicon for the outer portion of the gate insulating layer, patterning can be provided effectively. Moreover, since polysilicon initially is provided adjacent the gate insulating layer, stresses, cracking and/or defects may be reduced when thermally treating the gate electrode pattern to form the polysilicon gate.
The amorphous impurity layer may be formed by plasma processing the polysilicon layer opposite the gate insulating layer to amorphize the surface of the polysilicon layer opposite the gate insulating layer. Plasma processing may be performed using at least one of argon, xenon, helium and krypton. Alternatively, the amorphous impurity layer may be formed by implanting ions into the polysilicon layer opposite the gate insulating layer, to amorphize the surface of the polysilicon layer opposite the gate insulating layer. Implantation of silicon, germanium, indium, arsenic and/or antimony may be used.
The buried doped layer within the polysilicon gate electrode, that is spaced apart from the first and second surfaces thereof, preferably is formed from the amorphous impurity layer. During thermal treatment, diffusion of dopants generally takes place. Accordingly, the buried doped layer may be characterized by a dopant or impurity profile within the polysilicon gate electrode. For example, the polysilicon gate electrode has a doping concentration of at least one dopant that decreases from the buried doped layer towards the first surface and towards the second surface. Alternatively, the buried doped layer has doping concentration of at least one dopant that is higher than the doping concentration of the at least one dopant at the first and second surfaces of the polysilicon gate electrode. It will be understood that other dopants may be present in the polysilicon gate electrode that have uniform doping concentration in the polysilicon gate electrode. Alternatively, or in addition, other dopants may have nonuniform doping concentrations within the polysilicon gate electrode.
Intermediate product integrated circuit field effect transistors according to the present invention include spaced apart source and drain regions in an integrated circuit substrate and an insulated gate on the integrated circuit substrate between the spaced apart source and drain regions. The insulated gate preferably comprises a polysilicon layer on the gate insulating layer opposite the integrated circuit substrate, an amorphous impurity layer on the polysilicon layer opposite the gate insulating layer and an amorphous silicon layer on the amorphous impurity layer opposite the polysilicon layer. The amorphous impurity layer preferably comprises at least one of argon, xenon, helium, krypton, silicon, germanium, indium, arsenic and/or antimony.
Final product integrated circuit field effect transistors according to the present invention preferably include spaced apart source and drain regions in an integrated circuit substrate and an insulated gate on the integrated circuit substrate between the spaced apart source and drain regions. The insulated gate preferably comprises an insulating layer on the integrated circuit substrate and a polysilicon gate electrode having a first surface adjacent the gate insulating layer, a second surface opposite the gate insulating layer and a doping concentration of at least one dopant within the polysilicon gate electrode that decreases from within the polysilicon gate electrode towards the first surface and towards the second surface. Alternatively, the doping concentration of at least one dopant within the polysilicon gate electrode is higher within the polysilicon gate electrode than at the first and second surfaces of the polysilicon gate electrode. As described above, doping concentrations of other dopants may be uniform or nonuniform within the polysilicon gate electrode. Accordingly, integrated circuit field effect transistors can be formed that can have high performance and/or high reliability. It also will be understood that the present invention may be used to form other conductors for integrated circuits, such as conductive wiring layers, bit lines and the like.